Understanding Serial Communications > 자유게시판

To avoid contention on the RS485 bus, the application software must assure that only one transmitter is enabled at a time. These steps greatly reduce the chance that the communicating devices might be damaged by contention on the SPI bus. RS485Receive() to wait for any pending character transmission to complete, then disable the transmitter, and then execute a routine such as Key() to listen to the communications on the serial bus. These signals may alternatively be redirected to the digital inputs and outputs used by the second serial port if hardware handshaking is required. 12 volts and outputs logic level (0 or 5 volt) signals to the UART circuitry. The RS422 receiver converts the differential signal to the 0 to 5 volt logic signal required by the UART circuitry. Newer protocols include the full duplex RS422 and the half duplex RS485 protocols, each of which drives differential 0 to 5 volt signals on the serial cable. If your computer does not have an RS232 serial port, low cost USB-to-RS232 serial cables are available; contact Mosaic Industries for details. In the most common multi-drop RS-485 protocol, one computer is designated as a "master" and the rest of the computers or devices on the serial bus are designated as "slaves".

From the PDQ Board’s point of view, these three signals (/TxD, /RxD, and ground) are the only connections required to perform serial communications. Chassis and signal grounds are connected together to the digital ground (DGND) signal. By default, rs485 cable the RS485 connections are not brought out to the Docking Panel’s DB-9 Serial1 Connector. Done that establishes the RS485 receive mode is coded such that it waits until all queued (pending) characters have been transmitted before the driver chip is taken out of transmit mode. Each of the two channels on the UART Wildcard implements two 16-character FIFOs, one for outgoing characters and one for incoming characters. Characters may be lost if the transmit driver is turned off while pending characters are still being transmitted. Since both channels can operate simultaneously and independently, serial debugging can be performed while the application program is communicating via its primary channel. If your application requires RS485, you can use the secondary serial port (serial2) to program and debug your application code using the RS232 protocol, and use the primary serial port (Serial1) for RS485 communications. Because differential signals have inherently better signal-to-noise properties, reliable RS422 communications can be sent over much longer distances compared to RS232.

A modem (modulator/demodulator) provides a way of encoding digital data as a set of audio signals that can be sent over a telephone line. The UART Wildcard implements these optional RS232 modem handshaking signals on channel 1. The handshaking signals can be disabled and/or ignored by applications that do not need them. By connecting pairs of these handshaking signals together, the terminal or PC can be made to think that the PDQ Board is always ready to send and receive data. By connecting pairs of these handshaking signals together, the terminal or PC can be made to think that the QScreen Controller is always ready to send and receive data. In this manner, data can be exchanged between the master and each slave on the bus. The master can instruct a single slave to go into transmit mode, and then the master can put itself into receive mode, thereby allowing the master to retrieve data from the slave. The Serial2 channel is always configured for RS232 communications, and can sustain baud rates up to 4800 baud. A 2-wire synchronous IIC (Inter-IC) bus provides multi-drop signaling at rates up to 100 Kbaud. Each serial port can be configured for the RS232 or RS485 protocol, and runs at standard baud rates up to 115,200 bits per second.

Also, several non-serial interrupts can stack up; if they have higher priority than the serial interrupts, they will be serviced before the Serial2 interrupt routine, and again a serial input or output bit may be lost. If SPIF is set, reading the received data or initiating a new data transfer automatically clears the SPIF bit. The transmit and receive data signals carry the messages being communicated between the PDQ Board and the PC or terminal. The above parity settings will also determine how incoming data is interpreted (whether the most significant bit is considered a parity bit or part of the data being transmitted, and how many bits total to expect in each byte). Any of these conditions may generate an interrupt if the SPIE (SPI interrupt enable) bit in the SPCR control register is set. After configuring the SPI system to communicate on a properly connected network of devices, sending and receiving data is as simple as writing and reading a register. The master and slave could even exchange ascii QED-Forth operating system commands. Setting SPE (SPI enable) to 1 turns on the SPI system. If your application requires communicating with a device that expects to receive a parity bit, the generation of a parity bit and selection of even or odd parity, and whether there are seven or eight data bits in each byte, is performed by setting or clearing bits in the configuration registers SCI0CR1 for Serial1 and SCI1CR1 for Serial2.